As semiconductor devices, especially processors, have continued to increase in complexity and capability, they have also continued to require ever increasing amounts of power. Indeed, the amount of electrical current required in supplying power to such semiconductor devices has made it a commonplace practice to devote many of the pins, balls, pads or other types of interconnect (though it is common practice to use the term “pins” as engineering shorthand for the term “interconnect” regardless of whether the interconnects are truly pins or not) to ensure sufficient current capacity and adequate voltage.
FIG. 1 depicts a prior art pinout 100 for a semiconductor device. Specifically, FIG. 1 depicts the pinout used by Advanced Micro Devices of Sunnyvale, California for a series of processors. As shown, Vss interconnects 150 and Vcc interconnects 160 are dispersed throughout pinout 100. FIG. 2 depicts a prior art pinout 200 for another semiconductor device. Specifically, FIG. 2 depicts the pinout used by Intel Corporation of Santa Clara, Calif. for a different series of processors. Somewhat like the case in pinout 100, Vss interconnects 250 and Vcc interconnects 260 are dispersed through pinout 200.
As can be seen in both FIGS. 1 and 2, a large proportion of the available interconnects have been devoted to supplying power. However, the dispersion of both Vss and Vcc interconnects throughout pinouts 100 and 200 does not permit the use of large uninterrupted traces to carry power across a printed circuit board (PCB) from a power source to the Vss or Vcc interconnects of either pinouts 100 or 200. Furthermore, this same dispersion of both Vss and Vcc interconnects also results in any ground or power plane used to supply Vss and/or Vcc being so riddled with holes as to become too discontiguous to carry a large current with only low resistance. As those skilled in the art of PCB design will recognize, the sheer number of interconnects in semiconductor device pinouts, such as pinouts 100 and 200, requires that the interconnects be spaced closely together, which in turn requires that multiple layers of PCB traces be used to carry power and/or signals to and from these interconnects. This is the case regardless of whether a semiconductor device is attached to a PCB using current surfacemount or older through-hole approaches, because although the interconnects in surfacemount approaches don't penetrate through layers of a PCB, themselves, they require connections through vias that do.
With the use of either smaller traces or planes riddled with holes to supply power to semiconductor devices comes a corresponding increase in resistance, and this reduces the effectiveness of filtering capacitors placed adjacent to or in the middle of either pinouts 100 or 200. Transients caused by a semiconductor device and transmitted by one or more Vss and/or Vcc interconnects to a PCB are caused to last longer, have larger magnitudes, and not be as swiftly countered by filtering capacitors since these transients take longer than is often desirable to reach the filtering capacitors when propagating through traces and/or planes of such higher resistance. Furthermore, where a voltage regulator is used to supply power to a semiconductor device, these same traces and/or planes of such higher resistance result in changes in current requirements taking longer to be reflected at the output of even a voltage regulator located immediately adjacent to the semiconductor device, because the higher resistance does not allow the resulting change in voltage at the Vss and/or Vcc interconnects to propagate as quickly towards the output of the voltage regulator so that the voltage regulator may boost or lower its output as appropriate. Finally, the higher resistance results in more of the power meant for the semiconductor device to be lost as heat dissipated by the traces and/or planes.